In recent years, the amount of information that circuit devices handle has steadily grown, and printed circuit boards have increased in scale accompanied therewith. Increase in scale of printed circuit boards has also increased wiring volume between component pins, and design work volume has also become great. As a technique for making wiring work itself more efficient, techniques for automating wiring on printed circuit boards have frequently been proposed. However, with an initial wiring study stage, it is more important than wiring itself to effectively verify physical channel capacity used for a signal to be wired, and to suitably evaluate the number of substrate layers and an area used for the scale of a circuit to be designed appropriately and in short time. In particular, in the event of having performed bus signal wiring wherein multiple signal wires (nets) are wired between two components on a printed circuit board by being bundled, upon performing correction on bus signal wiring results, the entirety of the bus signal wiring may have to be corrected, and accordingly, such evaluation and study is important.
For example, description will be made regarding an example of a conventional wiring design technique wherein, as illustrated in FIG. 24, wiring between component pins (terminals) pa of a component A and component pins (terminals) pb of a component B is performed on a printed circuit board. With the example illustrated in FIG. 24, wiring design is performed so that nine pins pa of the component A, and nine pins pb of the component B are connected by nine signal wires (nets). Here, six wires on the upper side (see solid lines) of the nine signal wires are signal wires to be wired in parallel conforming to a first wiring rule (line width, gap), and three wires on the lower side (see dotted lines) of the nine signal wires are signal wires to be wired in parallel conforming to a second wiring rule different from the first wiring rule.
With an example of the conventional wiring design technique illustrated in FIG. 24, in the event that signal wires are wired in parallel between the component A and component B, study is performed at each of Section 1, Section 2, and Section 3, and all of detailed wirings (actual patterns) from the component pins pa to the component pins pb are generated. With Section 1, study is performed regarding wiring for leading out nets from the component pins pa out of the component A in accordance with a net alignment sequence. Similarly, with Section 3, study is performed regarding wiring for leading out nets from the component pins pb out of the component B in accordance with the net alignment sequence. Also, with Section 2, study is performed regarding wiring capacitance for wiring nine nets while avoiding a wiring prohibited area (obstruction) out of the components A and B.
More specifically, with an example of the conventional wiring design technique illustrated in FIG. 24, after lead wiring is performed in Section 1 and Section 3, parallel wiring between lead wires in the components A and B, i.e., in Section 2 is performed, and all of the patterns from the component pins pa to the component pins pb are generated. The lead wiring in Section 1 and Section 3 takes time and trouble due to adjustment of net alignment sequences. On the other hand, in the event that leading out of nets is performed in the coordinated net alignment sequences in Section 1 and Section 3, parallel wiring to be performed in Section 2 is executed in short time with comparatively small time and effort.
At this time, in the event that lead wiring in Section 1 and Section 3 is automatically performed, the alignment sequence of the led out nets may frequently be against a designer's intention. In such a case, lead wiring in Section 1 and Section 3 is repeatedly performed, and consequently, it takes a great amount of time on lead wiring processing in Section 1 and Section 3.
Also, in the event that after all of the patterns from the component pins pa to the component pins pb are once generated, restudy of wiring is performed by changing the net alignment sequence, lead wiring in Section 1 and Section 3 has to be repeatedly performed each time thereof. Therefore, it takes a great amount of time for processing to generate all of the patterns.
Next, another example of a conventional wiring design technique will be described with reference to FIGS. 25A and 25B. With the example illustrated in FIGS. 25A and 25B as well, in the same way as with the example illustrated in FIG. 24, description will be made regarding a case where wiring is performed between the component pins pa of the component A, and the component pins pb of the component B. With the example illustrated in FIGS. 25A and 25B, first, as illustrated in FIG. 25A, a heavy line indicating the nine signal wires (nets) in a pseudo manner is automatically wired between the components A and B. Upon the heavy line being wired, the heavy-line wiring in FIG. 25A is, as illustrated in FIG. 25B, automatically converted into detailed wirings which connects the component pins pa of the component A, and the component pins pb of the component B. At this time, though various techniques can be conceived as a conversion technique into detailed wirings, many techniques connect the corresponding terminals pa and pb, and accordingly, detour wiring is performed wherein the alignment sequence of the terminals pa of the component A, and the alignment sequence of the terminals pb of the component B are taken into consideration. Note that, in FIG. 25B, only detailed wirings on the component A side are illustrated, and drawing of detailed wirings on the component B side is omitted.
Therefore, with the other example of a conventional wiring design technique illustrated in FIGS. 25A and 25B, the heavy-line wiring illustrated in FIG. 25A and the detailed wirings illustrated in FIG. 25B are not simultaneously displayed. That is to say, the designer does not perform study with reference to the heavy-line wiring illustrated in FIG. 25A and the detailed wirings illustrated in FIG. 25B simultaneously, and does not perform study of wiring capacitance strictly.
Also, it takes a great amount of time to perform detour wiring processing on the component A side and component B side. Further, in the event that after performing conversion from the heavy-line wiring to the detailed wirings, change of the detailed wirings is performed, each time thereof, processing has to be repeatedly performed wherein heavy-line wiring is performed, detour wiring is performed, and conversion into detailed wirings is performed. Therefore, even with the technique illustrated in FIGS. 25A and 25B, it takes a great amount of time to perform processing for generating all of the patterns.
Japanese Laid-open Patent Publication Nos. 2002-124571, 03-237566, 01-154531, 2005-309871, and 2009-122764 are examples of the related art.